This invention relates to a multi-level, coplanar interconnect structure on an integrated circuit and, more particularly, to a hybrid dielectric structure for improving stiffness of back end of the line structures.
Continued improvement in integrated circuit density is due, in part, to advances in interconnection technology. IC manufacturing generally includes front end of the line (FEOL) and back end of the line (BEOL) processes. The FEOL processes relate to formation of transistors and capacitors and the like along with polysilicon gate layers. BEOL processes include steps to form metal interconnects and associated dielectrics. Conventional interconnect structures used aluminum for conductors. The aluminum was deposited as a film and then patterned to form interconnects. The dielectric insulation material was then added and planarized.
More recently, processes using copper interconnects have been developed. One such process uses damascene copper electroplating for chip interconnections. This process initially forms a planar insulation layer. The insulation layer is etched to form trenches or vias which are then filled with metal and polished to planarize. In a dual damascene process two patterns are combined into one.
The transition from aluminum to copper interconnects has resulted in reduction in resistance of interconnects. To reduce RC noise, dielectric materials having low dielectric constants ( also referred to as xe2x80x9clow kxe2x80x9d) are now being integrated into BEOL structures. However, low k dielectric materials are not generally structural in nature. They can not support applied loads encountered during wire bonding or ball bonding without adversely affecting the electrical reliability of the device. However, these changes must be addressed as the industry changes from quartz which has a high elastic modulus to low modulus materials used as dielectrics.
The present invention is directed to overcoming one or more of the problems discussed above, in a novel and simple manner.
In accordance with the invention, a hybrid dielectric interconnect structure using low k dielectric materials utilizes low modulus dielectric materials at the line level where noise is most likely, and higher elastic modulus dielectric materials which are structural in nature at the via levels.
Broadly, there is disclosed herein a multi-level, coplanar interconnect structure on an integrated circuit chip including a planar line layer having plural interconnect conductors separated by a dielectric material having a relatively low dielectric constant and a relatively low elastic modulus. A planar via layer comprises a dielectric film having an elastic modulus higher than in the line layer and conductive vias therethrough. One of the line and via layer is on an integrated circuit substrate and defines a first layer and the other of the line and via layer is on the first layer so that the vias are selectively in contact with the line layer conductors.
It is a feature of the invention that the dielectric film has a relatively low dielectric constant.
It is another feature of the invention that the dielectric material has a dielectric constant less than about 3.0.
It is another feature of the invention that the dielectric material comprises a polyarylene ether material.
It is still another feature of the invention that the dielectric material comprises an organic or an inorganic material. The dielectric film comprises an inorganic thin film.
It is yet another feature of the invention that the dielectric film comprises SiCOH film.
There is disclosed in accordance with another aspect of the invention, a multi-level, coplanar copper damascene interconnect structure on an integrated circuit chip including a first planar interconnect layer on an integrated circuit substrate and having plural line conductors separated by a dielectric material having a relatively low dielectric constant and a relatively low elastic modulus. A second planar interconnect layer on the first planar interconnect layer comprises a dielectric film having an elastic modulus higher than in the first planar interconnect layer and conductive vias therethrough. The vias are selectively in contact with the line conductors. A third planar interconnect layer on the second planar interconnect layer has plural line conductors separated by the dielectric material and selectively in contact with the vias.
There is disclosed in accordance with a further aspect of the invention a multi-level, coplanar interconnect structure on an integrated circuit chip including a planar line layer having plural interconnect conductors separated by an organic or inorganic dielectric material having a relatively low dielectric constant. A planar via layer comprises an inorganic dielectric film having a relatively low dielectric constant and conductive vias therethrough. One of the line and via layer is on an integrated circuit substrate and defines a first layer and the other of the line and via layer is on the first layer so that the vias are selectively in contact with the line layer conductors.
Further features and advantages of the invention will be readily apparent from the specification and from the drawings.